Texas Instruments AFE79 Series User Manual

www.ti.com DAC JESD Register Map
365
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-488. Register 143 Field Descriptions (continued)
Bit Field Type Reset Description
3-2
CTRL_TX2_DUC_
CLK_P1
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
1-0
CTRL_TX2_DUC_
CLK_P0
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
2.4.256 Register 144h (offset = 144h) [reset = 0h]
Figure 2-485. Register 144h
7 6 5 4 3 2 1 0
CTRL_TX1_JESD_CLK_P3 CTRL_TX1_JESD_CLK_P2 CTRL_TX1_JESD_CLK_P1 CTRL_TX1_JESD_CLK_P0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-489. Register 144 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_TX1_JESD_
CLK_P3
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
5-4
CTRL_TX1_JESD_
CLK_P2
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
3-2
CTRL_TX1_JESD_
CLK_P1
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
1-0
CTRL_TX1_JESD_
CLK_P0
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
2.4.257 Register 145h (offset = 145h) [reset = 0h]
Figure 2-486. Register 145h
7 6 5 4 3 2 1 0
CTRL_TX2_JESD_CLK_P3 CTRL_TX2_JESD_CLK_P2 CTRL_TX2_JESD_CLK_P1 CTRL_TX2_JESD_CLK_P0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-490. Register 145 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_TX2_JESD_
CLK_P3
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
5-4
CTRL_TX2_JESD_
CLK_P2
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
3-2
CTRL_TX2_JESD_
CLK_P1
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
1-0
CTRL_TX2_JESD_
CLK_P0
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English