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Texas Instruments AFE79 Series - 2.3.30 Register 44 h (offset = 44 h) [reset = 50 h]; 2.3.31 Register 45 h (offset = 45 h) [reset = FAh]

Texas Instruments AFE79 Series
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JESD_SUBCHIP Register Map
www.ti.com
178
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.3.30 Register 44h (offset = 44h) [reset = 50h]
Figure 2-71. Register 44h
7 6 5 4 3 2 1 0
MUX_SEL_FBAB_Q1_FOR_2R1
F_AB
MUX_SEL_FBAB_I1_FOR_2R1F
_AB
MUX_SEL_FBAB_Q0_FOR_2R1
F_AB
MUX_SEL_FBAB_I0_FOR_2R1F
_AB
R/W-1h R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-74. Register 44 Field Descriptions
Bit Field Type Reset Description
7-6
MUX_SEL_FBAB_
Q1_FOR_2R1F_A
B
R/W 1h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbab_3
0 : fbab_q_s0
1 : fbab_q_s1
2 : fbcd_q_s0
3 : fbcd_q_s1
Using LATTE to configure this register is recommended.
5-4
MUX_SEL_FBAB_I
1_FOR_2R1F_AB
R/W 1h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbab_2
0 : fbab_i_s0
1 : fbab_i_s1
2 : fbcd_i_s0
3 : fbcd_i_s1
Using LATTE to configure this register is recommended.
3-2
MUX_SEL_FBAB_
Q0_FOR_2R1F_A
B
R/W 0h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbab_1
0 : fbab_q_s0
1 : fbab_q_s1
2 : fbcd_q_s0
3 : fbcd_q_s1
Using LATTE to configure this register is recommended.
1-0
MUX_SEL_FBAB_I
0_FOR_2R1F_AB
R/W 0h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbab_0
0 : fbab_i_s0
1 : fbab_i_s1
2 : fbcd_i_s0
3 : fbcd_i_s1
Using LATTE to configure this register is recommended.
2.3.31 Register 45h (offset = 45h) [reset = FAh]
Figure 2-72. Register 45h
7 6 5 4 3 2 1 0
MUX_SEL_FBCD_Q1_FOR_2R1
F_AB
MUX_SEL_FBCD_I1_FOR_2R1
F_AB
MUX_SEL_FBCD_Q0_FOR_2R1
F_AB
MUX_SEL_FBCD_I0_FOR_2R1
F_AB
R/W-3h R/W-3h R/W-2h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

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