Texas Instruments AFE79 Series - 2.6.111 Register 49 CAh (offset = 49 CAh) [reset = 80 h]; 2.6.112 Register 49 CBh (offset = 49 CBh) [reset = 80 h]; 2.6.113 Register 49 CCh (offset = 49 CCh) [reset = 80 h]; 2.6.114 Register 49 CDh (offset = 49 CDh) [reset = 80 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.6.111 Register 49CAh (offset = 49CAh) [reset = 80h]
Figure 2-825. Register 49CAh
7 6 5 4 3 2 1 0
TX_VREG_IBIA
S_LANE3[0]
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-831. Register 49CA Field Descriptions
Bit Field Type Reset Description
7-7
TX_VREG_IBIAS_
LANE3[0]
R/W 1h
This register is effective only when per-lane register 0xF4[9]=1
(pu_himode_vddr)
2.6.112 Register 49CBh (offset = 49CBh) [reset = 80h]
Figure 2-826. Register 49CBh
7 6 5 4 3 2 1 0
TX_VREG_IBIAS_LANE2 TX_VREG_IBIAS_LANE3[2:1]
R/W-4h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-832. Register 49CB Field Descriptions
Bit Field Type Reset Description
7-5
TX_VREG_IBIAS_
LANE2
R/W 4h
This register is effective only when per-lane register 0xF4[9]=1
(pu_himode_vddr)
1-0
TX_VREG_IBIAS_
LANE3[2:1]
R/W 0h
This register is effective only when per-lane register 0xF4[9]=1
(pu_himode_vddr)
2.6.113 Register 49CCh (offset = 49CCh) [reset = 80h]
Figure 2-827. Register 49CCh
7 6 5 4 3 2 1 0
TX_VREG_IBIA
S_LANE1[0]
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-833. Register 49CC Field Descriptions
Bit Field Type Reset Description
7-7
TX_VREG_IBIAS_
LANE1[0]
R/W 1h
This register is effective only when per-lane register 0xF4[9]=1
(pu_himode_vddr)
2.6.114 Register 49CDh (offset = 49CDh) [reset = 80h]
Figure 2-828. Register 49CDh
7 6 5 4 3 2 1 0
TX_VREG_IBIAS_LANE0 TX_VREG_IBIAS_LANE1[2:1]
R/W-4h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset