Texas Instruments AFE79 Series - 2.3.36 Register 4 Ah (offset = 4 Ah) [reset = 54 h]; 2.3.37 Register 4 Bh (offset = 4 Bh) [reset = 76 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-79. Register 49 Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH3_
SEL
R/W 3h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX4.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2-0
TXOCTETPATH2_
SEL
R/W 2h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX3.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2.3.36 Register 4Ah (offset = 4Ah) [reset = 54h]
Figure 2-77. Register 4Ah
7 6 5 4 3 2 1 0
TXOCTETPATH5_SEL TXOCTETPATH4_SEL
R/W-5h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-80. Register 4A Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH5_
SEL
R/W 5h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX6.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2-0
TXOCTETPATH4_
SEL
R/W 4h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX5.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2.3.37 Register 4Bh (offset = 4Bh) [reset = 76h]
Figure 2-78. Register 4Bh
7 6 5 4 3 2 1 0
TXOCTETPATH7_SEL TXOCTETPATH6_SEL
R/W-7h R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset