Texas Instruments AFE79 Series - 2.3.89 Register A1 h (offset = A1 h) [reset = 20 h]; 2.3.90 Register A4 h (offset = A4 h) [reset = 10 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-132. Register A0 Field Descriptions (continued)
Bit Field Type Reset Description
5-5
TX_CLK_SYSREF
_SEL
R/W 0h select spi-based sysref which is tx_clk_sysref_val
4-2
TX_CLK_SYSREF
_DELAY
R/W 0h delaying the sysref to the dithered clock generation
1-1
TX_CLK_DITHERE
D_MODE_EN
R/W 1h
set to 1 for dithering the clocks derieved from root-clk
0 : Disable clk dither
1 : Enable clk dither
0-0 TX_CLK_DISABLE R/W 0h
Disable clk-generation from this module
0 : Enable
1 : Disable
2.3.89 Register A1h (offset = A1h) [reset = 20h]
Figure 2-130. Register A1h
7 6 5 4 3 2 1 0
TX_CLK_DIV4_
COMMON_PH
ASE_DISABLE
TX_CLK_DIV4_
PHASE4_DISA
BLE
TX_CLK_DIV4_
PHASE3_DISA
BLE
TX_CLK_DIV4_
PHASE2_DISA
BLE
TX_CLK_DIV4_
PHASE1_DISA
BLE
TX_CLK_DIV4_
PHASE0_DISA
BLE
TX_CLK_DIV4_
MULTIPHASE_
DISABLE
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-133. Register A1 Field Descriptions
Bit Field Type Reset Description
6-6
TX_CLK_DIV4_CO
MMON_PHASE_DI
SABLE
R/W 0h
setting this to '1' will disable all clk-phases
0 : Enable
1 : Disable
5-5
TX_CLK_DIV4_PH
ASE4_DISABLE
R/W 1h
setting this to '1' will disable clock div8_phase4
0 : Enable
1 : Disable
4-4
TX_CLK_DIV4_PH
ASE3_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase3
0 : Enable
1 : Disable
3-3
TX_CLK_DIV4_PH
ASE2_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase2
0 : Enable
1 : Disable
2-2
TX_CLK_DIV4_PH
ASE1_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase1
0 : Enable
1 : Disable
1-1
TX_CLK_DIV4_PH
ASE0_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase0
0 : Enable
1 : Disable
0-0
TX_CLK_DIV4_MU
LTIPHASE_DISAB
LE
R/W 0h
0 - div8 clocks will have 4 clock-phases
1 - div8 clocks will have a single-phase
0 : Enable multi-phase
1 : Disable multi-phase
2.3.90 Register A4h (offset = A4h) [reset = 10h]
Figure 2-131. Register A4h
7 6 5 4 3 2 1 0
RX_CLK_DIV_VAL_ACC_THRESH
R/W-10h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset