Timing Controller Register Map
www.ti.com
974
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-2268. Register BA Field Descriptions
Bit Field Type Reset Description
3-0
FORCE_FBNCOS
EL_CD
R/W 0h
This may be used in the shared tdd mode to distinguish
between fbncosel and rxncosel. Program this to "1000" to
make fb look differently from rx.
2.15.47 Register BCh (offset = BCh) [reset = 0h]
Figure 2-2254. Register BCh
7 6 5 4 3 2 1 0
ENABLE_FBNCOSEL_AB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2269. Register BC Field Descriptions
Bit Field Type Reset Description
3-0
ENABLE_FBNCOS
EL_AB
R/W 0h
bit mask for the 4 bit fbncosel_ab. If a particular bit is not
enabled, then 0 is sent, else the input fbncosel bit is sent
2.15.48 Register BDh (offset = BDh) [reset = 0h]
Figure 2-2255. Register BDh
7 6 5 4 3 2 1 0
ENABLE_FBNCOSEL_CD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2270. Register BD Field Descriptions
Bit Field Type Reset Description
3-0
ENABLE_FBNCOS
EL_CD
R/W 0h
bit mask for the 4 bit fbncosel_cd. If a particular bit is not
enabled, then 0 is sent, else the input fbncosel bit is sent
2.15.49 Register C0h (offset = C0h) [reset = 1h]
Figure 2-2256. Register C0h
7 6 5 4 3 2 1 0
DUAL_FBMOD
E
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2271. Register C0 Field Descriptions
Bit Field Type Reset Description
0-0 DUAL_FBMODE R/W 1h Choses whether single fb or dual fb
To Next Page
Loading...
Need help?
General
