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SBAU337–May 2020
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Serial Interface Register Maps
2.14.64 Register 401h (offset = 401h) [reset = 0h]
Figure 2-1947. Register 401h
7 6 5 4 3 2 1 0
FB_AGC_LNA
RF_DETECT_
MODE
FB_AGC_LNA_
RF_ATTACK_E
N
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1961. Register 401 Field Descriptions
Bit Field Type Reset Description
1-1
FB_AGC_LNARF_
DETECT_MODE
R/W 0h
Indicates whether RF detector can be used for LNA control or
not.
0: used as fixed step attack detector; 1: used to control LNA
bypass
0-0
FB_AGC_LNA_RF
_ATTACK_EN
R/W 0h
Use to control whether LNA RF attack detector output is used
by AGC or not
0 : Disable
1 : Enable
2.14.65 Register 402h (offset = 402h) [reset = 0h]
Figure 2-1948. Register 402h
7 6 5 4 3 2 1 0
FB_AGC_EXT_
DVGA_CNTRL
_EN
FB_AGC_EXT_
LNA_CNTL_EN
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1962. Register 402 Field Descriptions
Bit Field Type Reset Description
1-1
FB_AGC_EXT_DV
GA_CNTRL_EN
R/W 0h
Indicates whether AGC can control External DVGA or not At
any point of time only either LNA or External DVGA can be
enabled (see rx_agc_ext_lna_cntrl_en above)
0 : Disable
1 : Enable
0-0
FB_AGC_EXT_LN
A_CNTL_EN
R/W 0h
Indicates whether AGC can control LNA or not. At any point of
time only either LNA or External DVGA can be enabled (see
rx_agc_ext_dvga_cntrl_en below)
0 : Disable
1 : Enable
2.14.66 Register 404h (offset = 404h) [reset = Ah]
Figure 2-1949. Register 404h
7 6 5 4 3 2 1 0
reserved FB_AGC_PWR
_DECAY_DET_
EN
FB_AGC_PWR
_ATTACK_DET
_EN
FB_AGC_SMA
LL_STEP_DEC
AY_DET_EN
FB_AGC_BIG_
STEP_DECAY
_DET_EN
FB_AGC_SMA
LL_STEP_ATT
ACK_DET_EN
FB_AGC_BIG_
STEP_ATTACK
_DET_EN
R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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