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ADC JESD Register Map
445
SBAU337–May 2020
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Serial Interface Register Maps
2.5.174 Register 100h (offset = 100h) [reset = 0h]
Figure 2-670. Register 100h
7 6 5 4 3 2 1 0
JESD_SYNC_STATE_LANE3 JESD_SYNC_STATE_LANE2 JESD_SYNC_STATE_LANE1 JESD_SYNC_STATE_LANE0
R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-675. Register 100 Field Descriptions
Bit Field Type Reset Description
7-6
JESD_SYNC_STA
TE_LANE3
R 0h
0 -SYNC
1 -ILA
2 - DATA
5-4
JESD_SYNC_STA
TE_LANE2
R 0h
0 -SYNC
1 -ILA
2 - DATA
3-2
JESD_SYNC_STA
TE_LANE1
R 0h
0 -SYNC
1 -ILA
2 - DATA
1-0
JESD_SYNC_STA
TE_LANE0
R 0h
0 -SYNC
1 -ILA
2 - DATA
2.5.175 Register 101h (offset = 101h) [reset = 0h]
Figure 2-671. Register 101h
7 6 5 4 3 2 1 0
JESD_PREV_SYNC_STATE_LA
NE3
JESD_PREV_SYNC_STATE_LA
NE2
JESD_PREV_SYNC_STATE_LA
NE1
JESD_PREV_SYNC_STATE_LA
NE0
R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-676. Register 101 Field Descriptions
Bit Field Type Reset Description
7-6
JESD_PREV_SYN
C_STATE_LANE3
R 0h
0 -SYNC
1 -ILA
2 - DATA
5-4
JESD_PREV_SYN
C_STATE_LANE2
R 0h
0 -SYNC
1 -ILA
2 - DATA
3-2
JESD_PREV_SYN
C_STATE_LANE1
R 0h
0 -SYNC
1 -ILA
2 - DATA
1-0
JESD_PREV_SYN
C_STATE_LANE0
R 0h
0 -SYNC
1 -ILA
2 - DATA
2.5.176 Register 102h (offset = 102h) [reset = 0h]
Figure 2-672. Register 102h
7 6 5 4 3 2 1 0
JESD_MISC_STATUS_LANE1 JESD_MISC_STATUS_LANE0
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset