JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.3.83 Register 9Bh (offset = 9Bh) [reset = 0h]
Figure 2-124. Register 9Bh
7 6 5 4 3 2 1 0
SLOW_CLK_CNT[15:8]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-127. Register 9B Field Descriptions
Bit Field Type Reset Description
7-0
SLOW_CLK_CNT[
15:8]
R 0h Slow clock count value. MSB bit is ignored.
2.3.84 Register 9Ch (offset = 9Ch) [reset = 3h]
Figure 2-125. Register 9Ch
7 6 5 4 3 2 1 0
RX_CLK_LFSR
_SEED_LOAD
RX_CLK_SYS
REF_VAL
RX_CLK_SYS
REF_SEL
RX_CLK_SYSREF_DELAY RX_CLK_DITH
ERED_MODE_
EN
RX_CLK_DISA
BLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-128. Register 9C Field Descriptions
Bit Field Type Reset Description
7-7
RX_CLK_LFSR_S
EED_LOAD
R/W 0h
Loads the LFSR seed value when this is set to 1. Need to be
used along with 'tx_clk_lfsr_seed_val' register
0 : Use default LFSR seed value
1 : Load LFSR seed value from register
6-6
RX_CLK_SYSREF
_VAL
R/W 0h spi-based sysref
5-5
RX_CLK_SYSREF
_SEL
R/W 0h select spi-based sysref which is rx_clk_sysref_val
4-2
RX_CLK_SYSREF
_DELAY
R/W 0h delaying the sysref to the dithered clock generation
1-1
RX_CLK_DITHER
ED_MODE_EN
R/W 1h
set to 1 for dithering the clocks derieved from root-clk
0 : Disable clk dither
1 : Enable clk dither
0-0 RX_CLK_DISABLE R/W 1h
Disable clk-generation from this module
0 : Enable
1 : Disable
2.3.85 Register 9Dh (offset = 9Dh) [reset = 20h]
Figure 2-126. Register 9Dh
7 6 5 4 3 2 1 0
RX_CLK_DIV4
_COMMON_P
HASE_DISABL
E
RX_CLK_DIV4
_PHASE4_DIS
ABLE
RX_CLK_DIV4
_PHASE3_DIS
ABLE
RX_CLK_DIV4
_PHASE2_DIS
ABLE
RX_CLK_DIV4
_PHASE1_DIS
ABLE
RX_CLK_DIV4
_PHASE0_DIS
ABLE
RX_CLK_DIV4
_MULTIPHASE
_DISABLE
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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