IO Wrap Register Map
www.ti.com
1156
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.16.476 Register 8A5h (offset = 8A5h) [reset = 2h]
Figure 2-2739. Register 8A5h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_ADC_SYNC
_N_AB_1
OVR_INTPI_A
DC_SYNC_N_
AB_1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2755. Register 8A5 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
ADC_SYNC_N_AB
_1
R/W 1h
control to select whether the input function
intpi_adc_sync_n_ab_1 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_ADC_
SYNC_N_AB_1
R/W 0h
override value for ovr_sel_intpi_adc_sync_n_ab_1 is made
high
2.16.477 Register 8A8h (offset = 8A8h) [reset = 0h]
Figure 2-2740. Register 8A8h
7 6 5 4 3 2 1 0
SEL_INTPI_ADC_SYNC_N_AB_
2
POL_INTPI_AD
C_SYNC_N_A
B_2
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2756. Register 8A8 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_ADC_
SYNC_N_AB_2
R/W 0h
select control for intpi_adc_sync_n_ab_2. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_ADC_
SYNC_N_AB_2
R/W 0h
polarity control for intpi_adc_sync_n_ab_2. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.478 Register 8A9h (offset = 8A9h) [reset = 2h]
Figure 2-2741. Register 8A9h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_ADC_SYNC
_N_AB_2
OVR_INTPI_A
DC_SYNC_N_
AB_2
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2757. Register 8A9 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
ADC_SYNC_N_AB
_2
R/W 1h
control to select whether the input function
intpi_adc_sync_n_ab_2 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_ADC_
SYNC_N_AB_2
R/W 0h
override value for ovr_sel_intpi_adc_sync_n_ab_2 is made
high
To Next Page
Loading...
Need help?
General
