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JESD_SUBCHIP Register Map
191
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-97. Register 5E Field Descriptions
Bit Field Type Reset Description
6-4
ADC_JESD_SYNC
_N5_REORDER
R/W 5h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for sync_n broadcast to multiple lanes.
Using LATTE to configure this register is recommended.
2-0
ADC_JESD_SYNC
_N4_REORDER
R/W 4h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for sync_n broadcast to multiple lanes.
Using LATTE to configure this register is recommended.
2.3.54 Register 60h (offset = 60h) [reset = 10h]
Figure 2-95. Register 60h
7 6 5 4 3 2 1 0
MUX_SEL_FOR_TXB_CTRL MUX_SEL_FOR_TXA_CTRL
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-98. Register 60 Field Descriptions
Bit Field Type Reset Description
6-4
MUX_SEL_FOR_T
XB_CTRL
R/W 1h
Selects the OP_SAMP_MODE, 12B MODE and ALARMS that
are to be routed to jesd TXB
0 : sel from 2T0_TXA
1 : sel from 2T0_TXB
2 : sel from 2T0_TXC
3 : sel from 2T0_TXD
4 : sel from 2T1_TXA
5 : sel from 2T1_TXB
6 : sel from 2T1_TXC
7 : sel from 2T1_TXD
Using LATTE to configure this register is recommended.
2-0
MUX_SEL_FOR_T
XA_CTRL
R/W 0h
Selects the OP_SAMP_MODE, 12B MODE and ALARMS that
are to be routed to jesd TXA
0 : sel from 2T0_TXA
1 : sel from 2T0_TXB
2 : sel from 2T0_TXC
3 : sel from 2T0_TXD
4 : sel from 2T1_TXA
5 : sel from 2T1_TXB
6 : sel from 2T1_TXC
7 : sel from 2T1_TXD
Using LATTE to configure this register is recommended.
2.3.55 Register 61h (offset = 61h) [reset = 32h]
Figure 2-96. Register 61h
7 6 5 4 3 2 1 0
MUX_SEL_FOR_TXD_CTRL MUX_SEL_FOR_TXC_CTRL
R/W-3h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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