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List of Macros
81
SBAU337–May 2020
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Macro
Table 1-5. (continued)
Macro ADC Select configuration
2 0x01 1 Bit[1:0]:
0 → ADC4 is used for
2FB
1 → ADC5 is used for
2FB
2 → ADC6 is used for
2FB
3 → RESERVED
Bit[3:2]:
0 → ADC4 is used for
3RX
1 → ADC5 is used for
3RX
2 → ADC6 is used for
3RX
3 → RESERVED
Bit[5:4]:
0 → ADC4 is used for
4RX
1 → ADC5 is used for
4RX
2 → ADC6 is used for
4RX
3 → RESERVED
Bit[7:6]: RESERVED
Memory Not used
1.2.1.3 TDD/FDD Configuration
This Macro specifies whether the device is to operate in FDD mode or TDD mode. Each half (Core12 and
Core34) is independently configurable. Note that only in TDD mode do we allow sharing of ADC between
RX and FB channels.
Table 1-6. 5.2.2 TDD/FDD Configuration
Macro TDD / FDD Configuration
Opcode 0x22
Operand Offset Length Value Functionality Results
1 0x00 1 0x03 FDD for Core12 and
Core34
0x01 FDD for Core12 and
TDD for Core34
0x02 TDD for Core12 and
FDD for Core34
0x00 TDD for Core12 and
Core34
Memory Not used
1.2.1.3.1 Error Reporting
Table 1-7 lists the error conditions associated with this macro.
Table 1-7.
Error Status Registers Interpretation
Error Code 1 (16-bit) Bit[0]: ‘1’ → Invalid TDD/FDD mode argument
Error Code 2 (32-bit) Not Used
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