Texas Instruments AFE79 Series - 2.3.34 Register 48 h (offset = 48 h) [reset = 10 h]; 2.3.35 Register 49 h (offset = 49 h) [reset = 32 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-77. Register 47 Field Descriptions (continued)
Bit Field Type Reset Description
3-2
MUX_SEL_FBCD_
Q0_FOR_2R1F_C
D
R/W 0h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbcd_1
0 : fbcd_q_s0
1 : fbcd_q_s1
2 : fbab_q_s0
3 : fbab_q_s1
Using LATTE to configure this register is recommended.
1-0
MUX_SEL_FBCD_I
0_FOR_2R1F_CD
R/W 0h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbcd_0
0 : fbcd_i_s0
1 : fbcd_i_s1
2 : fbab_i_s0
3 : fbab_i_s1
Using LATTE to configure this register is recommended.
2.3.34 Register 48h (offset = 48h) [reset = 10h]
Figure 2-75. Register 48h
7 6 5 4 3 2 1 0
TXOCTETPATH1_SEL TXOCTETPATH0_SEL
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-78. Register 48 Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH1_
SEL
R/W 1h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX2.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2-0
TXOCTETPATH0_
SEL
R/W 0h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX0.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2.3.35 Register 49h (offset = 49h) [reset = 32h]
Figure 2-76. Register 49h
7 6 5 4 3 2 1 0
TXOCTETPATH3_SEL TXOCTETPATH2_SEL
R/W-3h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset