Texas Instruments AFE79 Series - 2.14.290 Register 5 E5 h (offset = 5 E5 h) [reset = 0 h]; 2.14.291 Register 5 E6 h (offset = 5 E6 h) [reset = 0 h]; 2.14.292 Register 5 E7 h (offset = 5 E7 h) [reset = 0 h]; 2.14.293 Register 5 E8 h (offset = 5 E8 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.14.290 Register 5E5h (offset = 5E5h) [reset = 0h]
Figure 2-2173. Register 5E5h
7 6 5 4 3 2 1 0
FB_AGC_MIN_ATTN_USED
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2187. Register 5E5 Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_MIN_AT
TN_USED
R 0h
Min attenuation seen by stat module. This is in 0.5 dB
resolution.
2.14.291 Register 5E6h (offset = 5E6h) [reset = 0h]
Figure 2-2174. Register 5E6h
7 6 5 4 3 2 1 0
FB_AGC_MAX_DVGA_ATTN_USED
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2188. Register 5E6 Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_MAX_DV
GA_ATTN_USED
R 0h
Max dvga attn seen by stat module. This is in 0.5 dB
resolution.
2.14.292 Register 5E7h (offset = 5E7h) [reset = 0h]
Figure 2-2175. Register 5E7h
7 6 5 4 3 2 1 0
FB_AGC_MIN_DVGA_ATTN_USED
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2189. Register 5E7 Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_MIN_DV
GA_ATTN_USED
R 0h
Min dvga attn seen by stat module. This is in 0.5 dB
resolution.
2.14.293 Register 5E8h (offset = 5E8h) [reset = 0h]
Figure 2-2176. Register 5E8h
7 6 5 4 3 2 1 0
reserved FB_AGC_BAN
D0_CURR_EX
T_LNA_BYPAS
S
FB_AGC_CURR_DVGA_ATTN
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset