SERDES Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.6.151 Register 49FFh (offset = 49FFh) [reset = 90h]
Figure 2-865. Register 49FFh
7 6 5 4 3 2 1 0
RX_PLL_BIAS1 PU_RX_BAND
GAP
R/W-4h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-871. Register 49FF Field Descriptions
Bit Field Type Reset Description
7-5 RX_PLL_BIAS1 R/W 4h Controls the RX PLL bias setting 1.
4-4 PU_RX_BANDGAP R/W 1h
Power up RX PLL bandgap
0h: Power down
1h: Power up
2.6.152 Register 6E01h (offset = 6E01h) [reset = 80h]
Figure 2-866. Register 6E01h
7 6 5 4 3 2 1 0
SRAM_ECC_E
N
SRAM_ECC_FORCE_ERR_TYP
E
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-872. Register 6E01 Field Descriptions
Bit Field Type Reset Description
7-7 SRAM_ECC_EN R/W 1h When set, enables SRAM ECC generation and checking
6-5
SRAM_ECC_FOR
CE_ERR_TYPE
R/W 0h
Allows for forcing SRAM ECC errors for debug:
00: No error
01: Complement bit 0 of SRAM input data (after ECC)
10: Complement bit 1 of SRAM input data (after ECC)
11: Complement bits 0 and 1 of SRAM input data (after ECC)
2.6.153 Register 6E03h (offset = 6E03h) [reset = 0h]
Figure 2-867. Register 6E03h
7 6 5 4 3 2 1 0
SRAM_ECC_C
ORR
SRAM_ECC_U
NCORR
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-873. Register 6E03 Field Descriptions
Bit Field Type Reset Description
7-7
SRAM_ECC_COR
R
R 0h
When set, an SRAM ECC correctable error has occurred.
Reading this register clears this bit.
6-6
SRAM_ECC_UNC
ORR
R 0h
When set, an SRAM ECC uncorrectable error has occurred.
Reading this register clears this bit.
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