Texas Instruments AFE79 Series - 2.5.118 Register ADh (offset = ADh) [reset = 20 h]; 2.5.119 Register AEh (offset = AEh) [reset = 0 h]; 2.5.120 Register AFh (offset = AFh) [reset = 0 h]; 2.5.121 Register B0 h (offset = B0 h) [reset = 0 h]

ADC JESD Register Map www.ti.com
426
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.5.118 Register ADh (offset = ADh) [reset = 20h]
Figure 2-614. Register ADh
7 6 5 4 3 2 1 0
LINK2_JESDV LINK2_ILA_S_M1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-619. Register AD Field Descriptions
Bit Field Type Reset Description
7-5 LINK2_JESDV R/W 1h JESD link config for STX 3,4/7,8
4-0 LINK2_ILA_S_M1 R/W 0h
JESD link config for STX 3,4/7,8
Used only when link2_jesd_ila_config_override is 1.
Else S derived from LMFS is used.
2.5.119 Register AEh (offset = AEh) [reset = 0h]
Figure 2-615. Register AEh
7 6 5 4 3 2 1 0
LINK2_ILA_HD 0 0 LINK2_CF
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-620. Register AE Field Descriptions
Bit Field Type Reset Description
7-7 LINK2_ILA_HD R/W 0h
JESD link config for STX 3,4/7,8
Used only when link2_jesd_ila_config_override is 1.
Else Hd derived from LMFS is used.
6-5 0 R/W 0h Must read or write 0
4-0 LINK2_CF R/W 0h JESD link config for STX 3,4/7,8
2.5.120 Register AFh (offset = AFh) [reset = 0h]
Figure 2-616. Register AFh
7 6 5 4 3 2 1 0
LINK2_RES1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-621. Register AF Field Descriptions
Bit Field Type Reset Description
7-0 LINK2_RES1 R/W 0h JESD link config for STX 3,4/7,8
2.5.121 Register B0h (offset = B0h) [reset = 0h]
Figure 2-617. Register B0h
7 6 5 4 3 2 1 0
LINK2_RES2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset