Texas Instruments AFE79 Series - 2.10.16 Register DDh (offset = DDh) [reset = 0 h]; 2.10.17 Register E0 h (offset = E0 h) [reset = 0 h]; 2.10.18 Register E1 h (offset = E1 h) [reset = 32 h]; 2.10.19 Register E4 h (offset = E4 h) [reset = 8 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.10.16 Register DDh (offset = DDh) [reset = 0h]
Figure 2-1122. Register DDh
7 6 5 4 3 2 1 0
PIN_AGC_MAX_DLY
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1132. Register DD Field Descriptions
Bit Field Type Reset Description
3-0
PIN_AGC_MAX_D
LY
R/W 0h
Configurable delay between update pin and actual capture in
cycles(in ADC_rate/4 clocks, eg- 750Mhz for 3Ghz ADC) in
pin based AGC mode.
2.10.17 Register E0h (offset = E0h) [reset = 0h]
Figure 2-1123. Register E0h
7 6 5 4 3 2 1 0
FDSA_PIN_UNCERT_CYC
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1133. Register E0 Field Descriptions
Bit Field Type Reset Description
2-0
FDSA_PIN_UNCE
RT_CYC
R/W 0h
Max expected uncertainity in cycles(in ADC_rate/4 clock
cycles) for FDSA.
2.10.18 Register E1h (offset = E1h) [reset = 32h]
Figure 2-1124. Register E1h
7 6 5 4 3 2 1 0
FDSA_MAX_ATTN
R/W-32h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1134. Register E1 Field Descriptions
Bit Field Type Reset Description
5-0 FDSA_MAX_ATTN R/W 32h Max gain value of FDSA setting.
2.10.19 Register E4h (offset = E4h) [reset = 8h]
Figure 2-1125. Register E4h
7 6 5 4 3 2 1 0
TM_PKDET_CUST_EXTEND_TIME
R/W-8h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset