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JESD_SUBCHIP Register Map
171
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-63. Register 35 Field Descriptions (continued)
Bit Field Type Reset Description
2-0
MUX_SEL_RXA_B
2_I_FOR_2R1F_A
B
R/W 2h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 rxa_2
0 : b1_rxa_i/rxa_i_s0
1 : b2_rxa_i/rxa_i_s1
2 : b1_rxb_i/rxb_i_s0
3 : b2_rxb_i/rxb_i_s1
4 : b1_rxc_i/rxc_i_s0
5 : b2_rxc_i/rxc_i_s1
6 : b1_rxd_i/rxd_i_s0
7 : b2_rxd_i/rxd_i_s1
Using LATTE to configure this register is recommended.
2.3.20 Register 36h (offset = 36h) [reset = 44h]
Figure 2-61. Register 36h
7 6 5 4 3 2 1 0
MUX_SEL_RXB_B1_Q_FOR_2R1F_AB MUX_SEL_RXB_B1_I_FOR_2R1F_AB
R/W-4h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-64. Register 36 Field Descriptions
Bit Field Type Reset Description
6-4
MUX_SEL_RXB_B
1_Q_FOR_2R1F_A
B
R/W 4h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 rxb_1
0 : b1_rxa_q/rxa_q_s0
1 : b2_rxa_q/rxa_q_s1
2 : b1_rxb_q/rxb_q_s0
3 : b2_rxb_q/rxb_q_s1
4 : b1_rxc_q/rxc_q_s0
5 : b2_rxc_q/rxc_q_s1
6 : b1_rxd_q/rxd_q_s0
7 : b2_rxd_q/rxd_q_s1
Using LATTE to configure this register is recommended.
2-0
MUX_SEL_RXB_B
1_I_FOR_2R1F_A
B
R/W 4h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 rxb_0
0 : b1_rxa_i/rxa_i_s0
1 : b2_rxa_i/rxa_i_s1
2 : b1_rxb_i/rxb_i_s0
3 : b2_rxb_i/rxb_i_s1
4 : b1_rxc_i/rxc_i_s0
5 : b2_rxc_i/rxc_i_s1
6 : b1_rxd_i/rxd_i_s0
7 : b2_rxd_i/rxd_i_s1
Using LATTE to configure this register is recommended.
2.3.21 Register 37h (offset = 37h) [reset = 66h]
Figure 2-62. Register 37h
7 6 5 4 3 2 1 0
MUX_SEL_RXB_B2_Q_FOR_2R1F_AB MUX_SEL_RXB_B2_I_FOR_2R1F_AB
R/W-6h R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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