Texas Instruments AFE79 Series User Manual

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459
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-714. Register 12C Field Descriptions
Bit Field Type Reset Description
7-7
MONITOR_JESD_
CLK_FB_P0
R 0h
Monitors the phase 0 clock status of JESD FB.
can be cleared by setting the CLEAR_JESD_CLK_FB_P0
register to 1
6-6
MONITOR_JESD_
CLK_RX2_P2
R 0h
Monitors the phase 2 clock status of JESD RX2.
Can be cleared by setting the CLEAR_JESD_CLK_RX2_P2
register to 1
5-5
MONITOR_JESD_
CLK_RX2_P0
R 0h
Monitors the phase 0 clock status of JESD RX2.
Can be cleared by setting the CLEAR_JESD_CLK_RX2_P0
register to 1
4-4
MONITOR_JESD_
CLK_RX1_P2
R 0h
Monitors the phase 2 clock status of JESD RX1.
Can be cleared by setting the CLEAR_JESD_CLK_RX1_P2
register to 1
3-3
MONITOR_JESD_
CLK_RX1_P0
R 0h
Monitors the phase 0 clock status of JESD Rx1.
Can be cleared by setting the CLEAR_JESD_CLK_RX1_P0
register to 1
2-2
MONITOR_DDC_R
D_CLK_FB
R 0h
Monitors the DDC read clock status of FB. Can be cleared by
setting the CLEAR_DDC_RD_CLK_FB register to 1
1-1
MONITOR_DDC_R
D_CLK_RX2
R 0h
Monitors the DDC read clock status of RXCD. Can be cleared
by setting the CLEAR_DDC_RD_CLK_RX2 register to 1
0-0
MONITOR_DDC_R
D_CLK_RX1
R 0h
Monitors the DDC read clock status of RXAB. Can be cleared
by setting the CLEAR_DDC_RD_CLK_RX1 register to 1
2.5.214 Register 12Dh (offset = 12Dh) [reset = 0h]
Figure 2-710. Register 12Dh
7 6 5 4 3 2 1 0
MONITOR_JES
D_CLK_RX2_P
0_MSF_RD
MONITOR_JES
D_CLK_RX1_P
0_MSF_RD
MONITOR_JES
D_CLK_DIV2_
FB_P3
MONITOR_JES
D_CLK_DIV2_
FB_P1
MONITOR_JES
D_CLK_DIV2_
RX2_P2
MONITOR_JES
D_CLK_DIV2_
RX1_P0
MONITOR_JES
D_CLK_FB_P3
MONITOR_JES
D_CLK_FB_P1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-715. Register 12D Field Descriptions
Bit Field Type Reset Description
7-7
MONITOR_JESD_
CLK_RX2_P0_MS
F_RD
R 0h UNUSED
6-6
MONITOR_JESD_
CLK_RX1_P0_MS
F_RD
R 0h UNUSED
5-5
MONITOR_JESD_
CLK_DIV2_FB_P3
R 0h
4-4
MONITOR_JESD_
CLK_DIV2_FB_P1
R 0h
3-3
MONITOR_JESD_
CLK_DIV2_RX2_P
2
R 0h
2-2
MONITOR_JESD_
CLK_DIV2_RX1_P
0
R 0h
1-1
MONITOR_JESD_
CLK_FB_P3
R 0h
Monitors the phase 3 JESD clock of FB.
Can be cleared by setting the CLEAR_JESD_CLK_FB_P3
register to 1
0-0
MONITOR_JESD_
CLK_FB_P1
R 0h
Monitors the phase 1 JESD clock of FB.
Can be cleared by setting the CLEAR_JESD_CLK_FB_P1
register to 1

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English