Texas Instruments AFE79 Series - 2.16.610 Register 10 C8 h (offset = 10 C8 h) [reset = 0 h]; 2.16.611 Register 10 C9 h (offset = 10 C9 h) [reset = 2 h]; 2.16.612 Register 10 F0 h (offset = 10 F0 h) [reset = 0 h]

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Serial Interface Register Maps
2.16.610 Register 10C8h (offset = 10C8h) [reset = 0h]
Figure 2-2873. Register 10C8h
7 6 5 4 3 2 1 0
POL_INTPO_D
AC_SYNC_N_
AB_1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2889. Register 10C8 Field Descriptions
Bit Field Type Reset Description
0-0
POL_INTPO_DAC
_SYNC_N_AB_1
R/W 0h
polarity control for intpo_dac_sync_n_ab_1. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.611 Register 10C9h (offset = 10C9h) [reset = 2h]
Figure 2-2874. Register 10C9h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PO_DAC_SYN
C_N_AB_1
OVR_INTPO_D
AC_SYNC_N_
AB_1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2890. Register 10C9 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPO_
DAC_SYNC_N_AB
_1
R/W 1h
control to select whether the input function
intpo_dac_sync_n_ab_1 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPO_DAC
_SYNC_N_AB_1
R/W 0h
override value for intpo_dac_sync_n_ab_1 when
ovr_sel_intpo_dac_sync_n_ab_1 is made high
2.16.612 Register 10F0h (offset = 10F0h) [reset = 0h]
Figure 2-2875. Register 10F0h
7 6 5 4 3 2 1 0
POL_INTPO_D
AC_SYNC_N_
CD_0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2891. Register 10F0 Field Descriptions
Bit Field Type Reset Description
0-0
POL_INTPO_DAC
_SYNC_N_CD_0
R/W 0h
polarity control for intpo_dac_sync_n_cd_0. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal