JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.3.51 Register 5Ch (offset = 5Ch) [reset = 10h]
Figure 2-92. Register 5Ch
7 6 5 4 3 2 1 0
ADC_JESD_SYNC_N1_REORDER ADC_JESD_SYNC_N0_REORDER
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-95. Register 5C Field Descriptions
Bit Field Type Reset Description
6-4
ADC_JESD_SYNC
_N1_REORDER
R/W 1h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for sync_n broadcast to multiple lanes
Using LATTE to configure this register is recommended.
2-0
ADC_JESD_SYNC
_N0_REORDER
R/W 0h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for sync_n broadcast to multiple lanes
Using LATTE to configure this register is recommended.
2.3.52 Register 5Dh (offset = 5Dh) [reset = 32h]
Figure 2-93. Register 5Dh
7 6 5 4 3 2 1 0
ADC_JESD_SYNC_N3_REORDER ADC_JESD_SYNC_N2_REORDER
R/W-3h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-96. Register 5D Field Descriptions
Bit Field Type Reset Description
6-4
ADC_JESD_SYNC
_N3_REORDER
R/W 3h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for sync_n broadcast to multiple lanes
Using LATTE to configure this register is recommended.
2-0
ADC_JESD_SYNC
_N2_REORDER
R/W 2h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for sync_n broadcast to multiple lanes
Using LATTE to configure this register is recommended.
2.3.53 Register 5Eh (offset = 5Eh) [reset = 54h]
Figure 2-94. Register 5Eh
7 6 5 4 3 2 1 0
ADC_JESD_SYNC_N5_REORDER ADC_JESD_SYNC_N4_REORDER
R/W-5h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset