ADC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-583. Register 85 Field Descriptions (continued)
Bit Field Type Reset Description
2-2
LINK0_DISABLE_F
_CHAR
R/W 0h
Config for STX1/5
Disable character replacement with CTRL_F for JESD-B
1-1
LINK0_DISABLE_A
_CHAR
R/W 0h
Config for STX1/5
Disable character replacement with CTRL_A for JESD-B
0-0
LINK0_NO_LANE_
SYNC
R/W 0h
Config for STX1/5
Set if lane synchronization is not supported. When set, ILA is
not transmitted
2.5.83 Register 86h (offset = 86h) [reset = 1h]
Figure 2-579. Register 86h
7 6 5 4 3 2 1 0
0 0 0 0 LINK0_SYNC_
F_CTR_INCR_
OVR_EN
LINK0_SYNC_F_CTR_INCR_OVR_VAL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-584. Register 86 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LINK0_SYNC_F_C
TR_INCR_OVR_E
N
R/W 0h
Config for STX1/5
To ovr, sync_n low duration check
2-0
LINK0_SYNC_F_C
TR_INCR_OVR_V
AL
R/W 1h
Config for STX1/5
When link0_sync_f_ctr_incr_ovr_en, sync_n low duration
counter is incremented with this spi value.
Can be 1 or 2 or 4
2.5.84 Register 87h (offset = 87h) [reset = 0h]
Figure 2-580. Register 87h
7 6 5 4 3 2 1 0
0 0 0 0 0 LINK0_JESD_TEST_SEQ_SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-585. Register 87 Field Descriptions
Bit Field Type Reset Description
7-3 0 R/W 0h Must read or write 0
2-0
LINK0_JESD_TES
T_SEQ_SEL
R/W 0h
JESD test sequence select for STX1/5
Test sequence select:
000=test sequence disabled
001=repeat /D.21.5/ high freq pattern for random jitter (RJ)
010=repeat /K.28.5/ mixed freq pattern for deterministic jitter
(DJ)
011=repeat initial lane alignment (ILA) sequence
100=modified random pattern (modified RPAT / CRPAT)
101=scrambled jitter pattern (JSPAT)
110=repeat /K.28.7/ low freq pattern
111=send short test pattern reg data