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Texas Instruments AFE79 Series - 2.4.253 Register 141 h (offset = 141 h) [reset = 0 h]; 2.4.254 Register 142 h (offset = 142 h) [reset = 0 h]; 2.4.255 Register 143 h (offset = 143 h) [reset = 0 h]

Texas Instruments AFE79 Series
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DAC JESD Register Map
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364
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.253 Register 141h (offset = 141h) [reset = 0h]
Figure 2-482. Register 141h
7 6 5 4 3 2 1 0
CTRL_TX2_ROOT_CLK_P3 CTRL_TX2_ROOT_CLK_P2 CTRL_TX2_ROOT_CLK_P1 CTRL_TX2_ROOT_CLK_P0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-486. Register 141 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_TX2_ROOT
_CLK_P3
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
5-4
CTRL_TX2_ROOT
_CLK_P2
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
3-2
CTRL_TX2_ROOT
_CLK_P1
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
1-0
CTRL_TX2_ROOT
_CLK_P0
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
2.4.254 Register 142h (offset = 142h) [reset = 0h]
Figure 2-483. Register 142h
7 6 5 4 3 2 1 0
CTRL_TX1_DUC_CLK_P3 CTRL_TX1_DUC_CLK_P2 CTRL_TX1_DUC_CLK_P1 CTRL_TX1_DUC_CLK_P0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-487. Register 142 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_TX1_DUC_
CLK_P3
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
5-4
CTRL_TX1_DUC_
CLK_P2
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
3-2
CTRL_TX1_DUC_
CLK_P1
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
1-0
CTRL_TX1_DUC_
CLK_P0
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
2.4.255 Register 143h (offset = 143h) [reset = 0h]
Figure 2-484. Register 143h
7 6 5 4 3 2 1 0
CTRL_TX2_DUC_CLK_P3 CTRL_TX2_DUC_CLK_P2 CTRL_TX2_DUC_CLK_P1 CTRL_TX2_DUC_CLK_P0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-488. Register 143 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_TX2_DUC_
CLK_P3
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN
5-4
CTRL_TX2_DUC_
CLK_P2
R/W 0h
bit[1] - select bit[0] as clk-en
bit[0] - 0:DIS, 1-EN

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