Texas Instruments AFE79 Series - 2.4.166 Register CEh (offset = CEh) [reset = 0 h]; 2.4.167 Register CFh (offset = CFh) [reset = 0 h]; 2.4.168 Register D0 h (offset = D0 h) [reset = 0 h]; 2.4.169 Register D1 h (offset = D1 h) [reset = 0 h]

www.ti.com DAC JESD Register Map
323
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.166 Register CEh (offset = CEh) [reset = 0h]
Figure 2-395. Register CEh
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT11[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-399. Register CE Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT11[7:0]
R/W 0h short test pattern input
2.4.167 Register CFh (offset = CFh) [reset = 0h]
Figure 2-396. Register CFh
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT11[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-400. Register CF Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT11[15:8]
R/W 0h short test pattern input
2.4.168 Register D0h (offset = D0h) [reset = 0h]
Figure 2-397. Register D0h
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT12[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-401. Register D0 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT12[7:0]
R/W 0h short test pattern input
2.4.169 Register D1h (offset = D1h) [reset = 0h]
Figure 2-398. Register D1h
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT12[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset