Texas Instruments AFE79 Series - 2.5.125 Register B6 h (offset = B6 h) [reset = 1 h]; 2.5.126 Register B7 h (offset = B7 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-625. Register B5 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LINK2_ENABLE_F
_CHAR_ON_MFE
ND
R/W 0h
config for STX 3,4/7,8
By default, don't send f_char on multiframe_end.
When 1, f_char is sen't on multiframe_end
2-2
LINK2_DISABLE_F
_CHAR
R/W 0h
config for STX 3,4/7,8
Disable character replacement with CTRL_F for JESD-B
1-1
LINK2_DISABLE_A
_CHAR
R/W 0h
config for STX 3,4/7,8
Disable character replacement with CTRL_A for JESD-B
0-0
LINK2_NO_LANE_
SYNC
R/W 0h
Controls lanes 0,1, or 4,5
Set if lane synchronization is not supported. When set, ILA is
not transmitted
2.5.125 Register B6h (offset = B6h) [reset = 1h]
Figure 2-621. Register B6h
7 6 5 4 3 2 1 0
0 0 0 0 LINK2_SYNC_
F_CTR_INCR_
OVR_EN
LINK2_SYNC_F_CTR_INCR_OVR_VAL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-626. Register B6 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LINK2_SYNC_F_C
TR_INCR_OVR_E
N
R/W 0h
Config for STX 3,4/7,8
To ovr, sync_n low duration check
2-0
LINK2_SYNC_F_C
TR_INCR_OVR_V
AL
R/W 1h
Config for STX 3,4/7,8
When link2_sync_f_ctr_incr_ovr_en, sync_n low duration
counter is incremented with this spi value.
Can be 1 or 2 or 4
This value is used a steps to increment sync_f counter which
checks sync inactive width of 4 or more
2.5.126 Register B7h (offset = B7h) [reset = 0h]
Figure 2-622. Register B7h
7 6 5 4 3 2 1 0
0 0 0 0 0 LINK2_JESD_TEST_SEQ_SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset