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FB Top Register Map
927
SBAU337–May 2020
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Serial Interface Register Maps
2.14.222 Register 545h (offset = 545h) [reset = 0h]
Figure 2-2105. Register 545h
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE4
[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2119. Register 545 Field Descriptions
Bit Field Type Reset Description
1-0
FB_AGC_BAND0_
LNA_PHASE4[9:8]
R/W 0h
LNA Phase for Band0 for temp index 4 in case of External
LNA Control , Phase for DVGA Index 4 in case of External
DVGA control
2.14.223 Register 546h (offset = 546h) [reset = 0h]
Figure 2-2106. Register 546h
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE5[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2120. Register 546 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BAND0_
LNA_PHASE5[7:0]
R/W 0h
LNA Phase for Band0 for temp index 5 in case of External
LNA Control , Phase for DVGA Index 5 in case of External
DVGA control
2.14.224 Register 547h (offset = 547h) [reset = 0h]
Figure 2-2107. Register 547h
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE5
[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2121. Register 547 Field Descriptions
Bit Field Type Reset Description
1-0
FB_AGC_BAND0_
LNA_PHASE5[9:8]
R/W 0h
LNA Phase for Band0 for temp index 5 in case of External
LNA Control , Phase for DVGA Index 5 in case of External
DVGA control
2.14.225 Register 548h (offset = 548h) [reset = 0h]
Figure 2-2108. Register 548h
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE6[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset