Texas Instruments AFE79 Series - 2.6.76 Register 40 AAh (offset = 40 AAh) [reset = 0 h]; 2.6.77 Register 40 ABh (offset = 40 ABh) [reset = 0 h]; 2.6.78 Register 40 ACh (offset = 40 ACh) [reset = 0 h]

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Serial Interface Register Maps
Table 2-795. Register 40A5 Field Descriptions
Bit Field Type Reset Description
3-0
READ_MRGN_CN
TR[11:8]
R 0h
Readout of Margin Counter module's output margin counter to
the state machine.
Margin loop counter readback value.
2.6.76 Register 40AAh (offset = 40AAh) [reset = 0h]
Figure 2-790. Register 40AAh
7 6 5 4 3 2 1 0
READ_PHASE_WANDER[7:0]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-796. Register 40AA Field Descriptions
Bit Field Type Reset Description
7-0
READ_PHASE_W
ANDER[7:0]
R 0h Timing loop phase wander readback value.
2.6.77 Register 40ABh (offset = 40ABh) [reset = 0h]
Figure 2-791. Register 40ABh
7 6 5 4 3 2 1 0
READ_PHASE_WANDER[14:8]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-797. Register 40AB Field Descriptions
Bit Field Type Reset Description
6-0
READ_PHASE_W
ANDER[14:8]
R 0h Timing loop phase wander readback value.
2.6.78 Register 40ACh (offset = 40ACh) [reset = 0h]
Figure 2-792. Register 40ACh
7 6 5 4 3 2 1 0
READ_RX_FREQ_ERROR[7:0]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-798. Register 40AC Field Descriptions
Bit Field Type Reset Description
7-0
READ_RX_FREQ_
ERROR[7:0]
R 0h
Read value of the RX frequency accumulator of format
S11.11. Each bit represents ~0.5ppm offset error between the
incoming traffic and the PLL.