Texas Instruments AFE79 Series - 2.4.137 Register B0 h (offset = B0 h) [reset = 0 h]; 2.4.138 Register B1 h (offset = B1 h) [reset = 0 h]; 2.4.139 Register B2 h (offset = B2 h) [reset = 0 h]

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Serial Interface Register Maps
2.4.137 Register B0h (offset = B0h) [reset = 0h]
Figure 2-366. Register B0h
7 6 5 4 3 2 1 0
JESDC_CMD_DATA[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-370. Register B0 Field Descriptions
Bit Field Type Reset Description
7-0
JESDC_CMD_DAT
A[7:0]
R/W 0h
JESDC:This pre-programmed spi register is to set the
command channel checker to check against the command
data stream from JESD 204C Tx IP of FPGA or ASIC.
JESDB : UNUSED
2.4.138 Register B1h (offset = B1h) [reset = 0h]
Figure 2-367. Register B1h
7 6 5 4 3 2 1 0
JESDC_CMD_DATA[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-371. Register B1 Field Descriptions
Bit Field Type Reset Description
7-0
JESDC_CMD_DAT
A[15:8]
R/W 0h
JESDC:This pre-programmed spi register is to set the
command channel checker to check against the command
data stream from JESD 204C Tx IP of FPGA or ASIC.
JESDB : UNUSED
2.4.139 Register B2h (offset = B2h) [reset = 0h]
Figure 2-368. Register B2h
7 6 5 4 3 2 1 0
JESDC_CMD_DATA[17:16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-372. Register B2 Field Descriptions
Bit Field Type Reset Description
1-0
JESDC_CMD_DAT
A[17:16]
R/W 0h
JESDC:This pre-programmed spi register is to set the
command channel checker to check against the command
data stream from JESD 204C Tx IP of FPGA or ASIC.
JESDB : UNUSED