Texas Instruments AFE79 Series User Manual

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.138 Register CAh (offset = CAh) [reset = 1h]
Figure 2-634. Register CAh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 SCR_64B_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-639. Register CA Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0 SCR_64B_EN R/W 1h
Used in JESD-C
To enable/disable 64 bit scrambler
(1+x^39+x^58)
1 : 64b scr enabled
0 : 64b scr disabled
2.5.139 Register CBh (offset = CBh) [reset = 0h]
Figure 2-635. Register CBh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 reserved SCR_64B_BIT_
SWAP_DISABL
E
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-640. Register CB Field Descriptions
Bit Field Type Reset Description
7-2 0 R/W 0h Must read or write 0
1-1 reserved R/W 0h
0-0
SCR_64B_BIT_SW
AP_DISABLE
R/W 0h
In JESD-C
By default, bit order is NOT reversed
When 1, bit order within each byte is reversed, before going to
64b scrambler
2.5.140 Register CCh (offset = CCh) [reset = 0h]
Figure 2-636. Register CCh
7 6 5 4 3 2 1 0
JESDC_CMD[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-641. Register CC Field Descriptions
Bit Field Type Reset Description
7-0 JESDC_CMD[7:0] R/W 0h
For JESD-C
6 bits corresponding to 6 command bits used in CRC and FEC
encoding.
All 18 bits are used in CMD encoding is used

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English