Texas Instruments AFE79 Series - 2.4.58 Register 59 h (offset = 59 h) [reset = Fh]; 2.4.59 Register 5 Ah (offset = 5 Ah) [reset = 2 Fh]; 2.4.60 Register 5 Bh (offset = 5 Bh) [reset = 20 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-290. Register 58 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_ILA_M_M1 R/W 1h
JESD M-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.58 Register 59h (offset = 59h) [reset = Fh]
Figure 2-287. Register 59h
7 6 5 4 3 2 1 0
LINK1_CS LINK1_ILA_N_M1
R/W-0h R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-291. Register 59 Field Descriptions
Bit Field Type Reset Description
7-6 LINK1_CS R/W 0h Lane configuration
4-0 LINK1_ILA_N_M1 R/W Fh
JESD N-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.59 Register 5Ah (offset = 5Ah) [reset = 2Fh]
Figure 2-288. Register 5Ah
7 6 5 4 3 2 1 0
LINK1_SUBCLASSV LINK1_ILA_NPRIME_M1
R/W-1h R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-292. Register 5A Field Descriptions
Bit Field Type Reset Description
7-5
LINK1_SUBCLASS
V
R/W 1h
Selects the JESD subclass. Note: '1' is subclass 1 and '0' is
subclass 0; they are the only modes supported; not used for
operation but used for configuration. See min_latency_ena for
use in subclass 0
4-0
LINK1_ILA_NPRIM
E_M1
R/W Fh
JESD N'-1 configuration value used only for ILA checking;
may be set independently of the actual JESD mode
2.4.60 Register 5Bh (offset = 5Bh) [reset = 20h]
Figure 2-289. Register 5Bh
7 6 5 4 3 2 1 0
LINK1_JESDV LINK1_ILA_S_M1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-293. Register 5B Field Descriptions
Bit Field Type Reset Description
7-5 LINK1_JESDV R/W 1h
Selects the version of JESD support
0=A
1=B
2=C