Texas Instruments AFE79 Series - Page 202

JESD_SUBCHIP Register Map www.ti.com
202
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-118. Register 91 Field Descriptions
Bit Field Type Reset Description
7-4
CFG_SLOW_CLK_
SEL
R/W 0h
Selection control for slow clock for inst0 or inst1
Clk-sel for INST0
0 : w_serdesab_mux_txbclk[0] Lane0 Serdes-ab-tx clk,
coming from lane-mux
1 : w_serdescd_mux_txbclk[0] Lane0 Serdes-cd-tx clk, coming
from lane-mux
2 : rx_adc_clk_div4[0] Dither rx div4 clk, phase-0
3 : tx_or_fb_adc_clk_div4[0] Dither tx or fb div4 clk, phase-0
4 : w_ddc_rd_clk_rxa ddc-jesd-fifo-rd clk for rxa
5 : w_ddc_rd_clk_rxb ddc-jesd-fifo-rd clk for rxb
6 : w_ddc_rd_clk_fbab ddc-jesd-fifo-rd clk for fbab
7 : adc_jesd_ab_clk_rx1_p0 Jesd-clk for rxa
8 : adc_jesd_ab_clk_rx2_p0 Jesd-clk for rxb
9 : adc_jesd_ab_clk_fb_p0 Jesd-clk for fbab
10 : w_rxa_adc_clk_dft[0] RRF_to_JESD clk for rxa
11 : w_rxc_adc_clk_dft[0] RRF_to_JESD clk for rxc
12 : w_fbab_adc_clk_dft[0] RRF_to_JESD clk for fbab
13 : w_fbcd_adc_clk_dft[0] RRF_to_JESD clk for fbcd
14 : w_ddc_rd_clk_rxc Jesd-clk for rxc
15 : w_ddc_rd_clk_fbcd Jesd-clk for fbcd
Clk-sel for INST1
0 : Lane0 Serdes-ab-rx clk, coming from lane-mux
1 : Lane0 Serdes-cd-rx clk, coming from lane-mux
2 : Dither tx div4 clk, phase-0
3: JESD_to_TXTOP clk for txa
4 : JESD_to_TXTOP clk for txb
5 : JESD_to_TXTOP clk for txc
6 : JESD_to_TXTOP clk for txd
7 : dac_jesd_ckl for txa
8 : dac_jesd_ckl for txb
9 : dac_jesd_ckl for txc
10 : dac_jesd_ckl for txd
11 : Jesd-clk for rxc
12 : Jesd-clk for rxd
13 : Jesd-clk for fbcd
14 : Direct GPIO clean clock
15 : APB clock used in spi2apb and as clock_bus to serdes