Texas Instruments AFE79 Series - Page 72

Addr OPERAND_BA
Addr STATUS_BA
Addr OPCODE_BA
Base address of Operand
Addr MACRO_ MEM_BA
Macro Memory
Operand
Trigger
Addr
OPERAND_BA
Burst Mode ++
Operand 0 Operand 1
Address
OPCODE_BA
Opcode
Address = OPERAND_BA
Op 1 Op 0
SPI Page Change
Macro Mem
DATA 0 DATA 1 DATA 2 DATA N-1
Addr
MACRO_MEM_BA
Burst Mode ++
Address = MACRO_MEM_BA
Data 0 Data 1
Data 2 Data 3
N-2 N-1
Address = OPCODE_BA
SPI Page Change
(Customer)
Base address of Status Registers
Base address of Opcode
Base address of Operand
Base address of Macro Memory
Legend
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72
SBAU337–May 2020
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Macro
Figure 1-6. SPI write sequence for initiating Macro with large data transfer mode