Peripherals Routed Through the DPI
A-244 ADSP-214xx SHARC Processor Hardware Reference
Table A-127. UART0LCR Register Bit Descriptions (RW)
Bit Name Description
1–0 UARTWLS Word Length Select.
00 = 5-bit word(UARTWLS5)
01 = 6-bit word(UARTWLS6)
10 = 7-bit word(UARTWLS7)
11 = 8-bit word(UARTWLS8)
2UARTSTBStop Bits.
0 = 1 stop bit
1 = 2 stop bits for non-5-bit word length or 1 1/2 stop bits for
5-bit word length
3UARTPENParity Enable.
0 = Parity not transmitted or checked
1 = Transmit and check parity
4UARTEPSEven Parity Select.
0 = Odd parity when PEN = 1 and STP = 0
1 = Even parity when PEN = 1 and STP = 0
5UARTSTPStick Parity.
Forces parity to defined value if set and PEN = 1.
0 = Parity transmitted and checked as 1
1 = Parity transmitted and checked as 0
6UARTSBSet Break. The UART transmit pin is driven high normally. This
bit is used to force the transmit pin to zero. This bit functions
even when the UART is not enabled. Using this bit the UART TX
pin can be used as a flag pin when the UART is not used.
0 = No force
1 = Force UART0Tx_O pin to 0.
7 UARTDLAB Divisor Latch Access Bit. Because some IOP registers share the
same address, this bit provides access as follows.
0 = Enable access to UART0THR, UART0RBR, and UART_IER
registers
1 = Enable access to UART0DLL and UARTxDLH registers
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