ADSP-214xx SHARC Processor Hardware Reference 21-13
Two Wire Interface Controller
rates and peripheral bus access times, a double byte transfer data access can
be performed. Two data bytes can be written, effectively filling the trans-
mit FIFO buffer with a single access.
The data is written in little-endian byte order where byte 0 is the first byte
to be transferred and byte 1 is the second byte to be transferred. With each
access, the transmit status (
TWITXS) field in the TWIFIFOSTAT register is
updated. If an access is performed while the FIFO buffer is not empty, the
core waits until the FIFO buffer is completely empty and then completes
the write access.
8-Bit Receive FIFO Register
The TWI 8-bit FIFO receive register (RXTWI8) shown in Figure 21-9 holds
an 8-bit data value read from the FIFO buffer. Receive data is read from
the corresponding receive buffer in a first-in, first-out order. Although
peripheral bus reads are 32 bits, a read access to the RXTWI8 register can
only access one receive data byte from the FIFO buffer. With each access,
the receive status (
TWIRXS) field in the TWIFIFOSTAT register is updated. If
an access is performed while the FIFO buffer is empty, the core waits until
there is at least one byte in the receive FIFO buffer and then completes the
read access.
Figure 21-8. 16-Bit Transmit FIFO Register
Figure 21-9. 8-Bit Receive FIFO Register
XMTDATA16 (7–0)
XMTDATA16 (23–16)
Byte0–Transmitted first
Byte1–Transmitted second
09 837564 2114 12 11 101315
RCVDATA8 (7–0)
Receive FIFO 8-bit Data
09 837564 2114 12 11 101315
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