ADSP-214xx SHARC Processor Hardware Reference A-31
Registers Reference
DDR2 Control Register 2 (DDR2CTL2)
Figure A-11 and Table A-13 show the DDR2 control register 2 bit defini-
tions. Values written into this register are loaded into the DDR2 mode
register during power up (or when
Force LMR bit in the DDR2CTL0 register is
set). This register should be initialized before starting the Initialization
sequence.
This register’s contents should not be changed while DDR2 inter-
face is active. Also whenever this register contents are changed a
initialization sequence must be executed to reflect this register con-
tents in to the DDR2 mode register.
24–22 DDR2TRRD Row to Row Activation Delay.
000 = Reserved.
001 = 1 clock cycle
010 = 2 clock cycles
…
111 = 7 clock cycles
29–25 DDR2TFAW Force Activation Window. For 8 banked devices up to 4
banks open in activation window. For 4 banked devices
the settings are ignored.
00000 = Reserved
00001 = 1 clock cycle
00010 = 2 clock cycles
…
11111 = 31 clock cycles
31–30 Reserved
Table A-12. DDR2CTL1 Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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