ADSP-214xx SHARC Processor Hardware Reference 16-23
Peripheral Timers
2. The
PRDCNT bit determines when the IRQ status bit (if enabled) is
set.
•If (PRDCNT == 1), IRQ is set when the period expires and the
value is captured.
•If (PRDCNT == 0), IRQ is set when the width expires and the
value is captured.
3. Valid period and width values are set in their respective registers
when IRQ is set.
The period and width values are measured with respect to PCLK.
This makes this mode coherent with the PWM_OUT mode, where
the output waveforms have a period of 2 x period and a width of 2
x width.
Note that the first period value will not have been measured when
the first width is measured, so it is not valid. The timer sets and
returns a period value of zero in this case. When the period expires,
the period value is placed into the period register. When IRQ is
sensed, read the status and perform the appropriate “write-one” to
clear.
EXT_CLK Mode
Use the following procedure to configure and run the timer in EXT_CLK
out mode.
1. Reset the TIMEN bit and set the configuration mode to 11 to select
EXT_CLK operation.
This configures the TIMERx_I pin as an input pin regardless of the
setting of the PULSE bit. Note that the timer always samples the ris-
ing edge in this mode. The period register is WO and the width
register is unused in this mode.
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