ADSP-214xx SHARC Processor Hardware Reference 10-35
Serial Ports
three-stated when the time slot is not active, the
SPORTx_TDV_0 signal spec-
ifies if the SPORT data is being driven by the processor.
Unlike previous SHARC processors, the assertion of the SPORTx_TDV_0 is
independent for the transmit buffer status (valid data or not). So writing
to the buffer does not affect the SPORTx_TDV_0 output timing.
Timing Control Bits
Several bits in the SPCTLx register enable and configure multichannel
mode.
• Frame Delay (MFD)
• Number of multichannel channels (NCH)
• Internal Clock (ICLK)
• Internal Frame Sync (IMFS)
• Sampling Edges Frame Sync/Data (CKRE)
• Logic Level Frame Sync (LMFS)
• Word Length (SLEN, 8–32 bits)
• Word Order (LSBF)
• Word Packing (
PACK)
Number of Channels (NCH)
Select the number of channels used in multichannel operation by using
the 7-bit
NCH field in the multichannel control register. Set NCH to the
actual number of channels minus one (
NCH = Number of channels – 1).
The 7-bit CHNL field in the multichannel control registers indicates the
channel that is currently selected during multichannel operation. This
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