Programming Models
3-132 ADSP-214xx SHARC Processor Hardware Reference
AMI Configuration
For instruction fetch, the original (logical) address is multiplied by 3/2
and this address is translated depending on the bus width and
PKDIS bit
setting.
1. Assign external bank0 to AMI in the EPCTL register (default).
2. Wait at least 8 CCLK cycles (effect latency).
3. Enable the global AMIEN bit and clear (=0) the PKDIS bit.
SDRAM Configuration
For instruction fetch, the original (logical) address is multiplied by 3/2
and this address is translated depending on the bus width setting (X16DE
bit).
1. Assign external bank 0 to SDRAM in the EPCTL register (default).
2. Wait at least 8 CCLK cycles (effect latency).
3. Configure the SDCTL and SDRRC registers accordingly.
External Memory Access Restrictions
The following external memory restrictions should be noted when writing
programs.
1. The LW mnemonic is not applicable to external memory.
2. Conditional accesses to external memory should not be based on
any of the FLAG pin status.
3. There is one cycle latency between a multiplier status change and
an arithmetic loop abort. This extra cycle is a machine cycle and
not the instruction cycle. Therefore, if there is a pipeline stall (due
to external memory access etc.) then the latency does not apply.
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