ADSP-214xx SHARC Processor Hardware Reference 6-45
FFT/FIR/IIR Hardware Modules
Interrupt Sources
There are two types of DMA interrupt sources associated with the acceler-
ator. The
FIR_CCINTR bit in the FIRCTL1 register controls these interrupts.
Window Complete Interrupt – This interrupt is generated at the end of
each channel when all the output samples are calculated corresponding to
a window and updated index values are written back.
All Channels Complete Interrupt – This interrupt is generated when all
the channels are complete or when one iteration of time slots completes.
MAC Status Interrupt – The status interrupt sources are derived from the
FIRMACSTAT register. For more information, see “FIR MAC Status Register
(FIRMACSTAT)” on page A-83.
Service Channel Interrupts – Based on the FIR_CCINTR bit in the FIRCTL1
register both bits (FIR_DMAWDONE or FIR_DMAACDONE) are set in the
FIRDMSTAT register if either of the conditions is met. The interrupt service
routine should read (to clear) both bits.
Service MAC Status Interrupts – A MAC status interrupt is generated
whenever a fixed or floating-point operation results in an arithmetic
exception. Reading the FIRMACSTAT register returns for which MAC unit is
causing an exception.
Debug Features
The following sections provide information of debugging the FIR
accelerator.
Local Memory Access
The contents of FIR delay line and coefficient memories are made observ-
able for debug by setting the FIR_DBGMODE/FIR_DBGMEM and FIR_HLD bits in
the
FIRDEBUGCTL control register. The debug address register
(FIR_DBGADDR) and two data registers are provided for debug operations.
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