Peripherals Routed Through the DPI
A-246 ADSP-214xx SHARC Processor Hardware Reference
Interrupt Enable Register (UART0IER)
The interrupt enable register (shown in Figure A-138) is used to enable
requests for system handling of empty or full states of UART data regis-
ters. Unless polling is used as a means of action, the
UARTRBFIE and/or
UARTTBEIE bits in this register are normally set.
4UARTBI Break Interrupt. The break interrupt (UARTBI), overrun error
(UARTOE), parity error (UARTPE), and framing error (UARTFE)
bits are cleared when the UART line status register (UART0LSR) is
read. The data ready (UARTDR) bit is cleared when the UART
receive buffer register (UART0RBR) is read.
0 = No break interrupt
1 = Break interrupt. This indicates Rx pin was held low for more
than the max word length.
5UARTTHREUARTx_THR Empty. The UARTTHRE bit indicates that the
UART transmit channel is ready for new data, and software can
write to the UARTxTHR register. Writes to UART0THR clear the
UARTTHRE bit. It is set again when data is copied from
UART0THR to the transmit shift register (UART0TSR). The
UARTTEMT bit can be evaluated to determine whether a recently
initiated transmit operation has been completed.
0 = Not empty
1 = Empty (default)
6UARTTEMTTSR and UART0_THR Empty.
0 = Full
1 = Both empty
7 UARTRX9D 9th bit of the received character-address detect
1 These bits are read-only in the UARTxLRSH (shadow) register.
Table A-128. UART0LSR Register Bit Descriptions (Cont’d)
Bit Name Description
To Next Page
Loading...
Need help?
General
