Clocking
9-4 ADSP-214xx SHARC Processor Hardware Reference
Pin Enable Signal Routing (SRU2_PBENx). Associated with group C
used to specify whether each DPI pin is used as an output or an input by
setting the source for the pin buffer enable.
The DAI/DPI registers are unique in that they work as groups to control
other peripheral functions. The register groups and routings are described
in detail in “DAI/DPI Group Routing” on page 9-18, “DAI Signal Rout-
ing Unit Registers” on page A-118 and “DPI Signal Routing Unit
Registers” on page A-218.
Clocking
The fundamental timing clock of the DAI/DPI modules is peripheral
clock/2 (PCLK/2).
Functional Description
Figure 9-1 shows how the DAI pin buffers are connected via the SRU.
This allows for very flexible signal routing.
The DAI/DPI is comprised of four primary blocks:
• Peripherals (A/B/C) associated with DAI/DPI
• Signal Routing Units (SRU, SRU2)
• DAI/DPI I/O pin buffers
• Miscellaneous buffers
The peripherals shown in Figure 9-1 can have up to three connections (if
master or slave capable); one acts as signal input, one as signal output and
the 3rd as output enable. The SRUs are based on a group of multiplexers
which are controlled by registers to establish the desired interconnects.
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