ADSP-214xx SHARC Processor Hardware Reference 20-21
UART Port Controller
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
UART Effect Latency
After the UART registers are configured the effect latency is 2 PCLK cycles.
Note that when transmitting data the effective data on DPI pins can’t be
seen immediately after 2 PCLK cycles because the time which the UART
takes to start driving data depends on the baud rate settings.
Programming Model
The following sections provide some programming procedures for core
and DMA data transfers.
Autobaud Detection
When the baud rate of the incoming signal is not known, one of the gen-
eral-purpose timers can be used in width capture mode to automatically
calculate the baud rate. Do not enable the UART until the width is cap-
tured by the timer. To perform autobaud detection, use the following
procedure.
1. The UART RX input signal is fed to a DPI pin buffer. This buffer
is used as an input (
DPI_PBENxx_I is low). The pin buffer output
(
DPI_PBxx_O) is routed to both inputs UART_RX_I and TIMERx_I.
2. Configure the timer in width capture mode with the timer inter-
rupt enabled. Inside the ISR, the program should read the width of
the incoming signal and disable the timer.
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