ADSP-214xx SHARC Processor Hardware Reference 6-69
FFT/FIR/IIR Hardware Modules
Writing to Local Memory
1. Enable IIR module in PMCTL1 register.
2. Wait at least 4
CCLK cycles.
3. Clear the
IIR_DMAEN bit in the IIRCTL1 register.
4. Set the
IIR_DBGMODE, IIR_DBGMEM and IIR_HLD bits in the IIRDE-
BUGCTL
register.
Figure 6-14. Biquad Processing Program Flow
Preload all the coefficients and
initialize intermediate results
Load TCB for current channel
All channels
done?
Wait for
core intervention
NO
YES
Process one window
of current channel
Move to next
channel
Core sets up control
register and initiates run
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