Peripherals Routed Through the DAI
A-206 ADSP-214xx SHARC Processor Hardware Reference
Receive Status Register (DIRSTAT)
The Status register consists of status bits (VALIDITY, NONAUDIO, NOSTREAM,
BIPHERR, PARITYERR and LOCK), indicate the status of various functions
supported by S/PDIF Receiver. It also has the lower byte of the 40-bit
channel status information. The
VALIDITY, NOSTREAM, BIPHERR, PARITYERR
and
LOCK bits are sticky and cleared on read. This register also contains the
lower byte of the 40-bit channel status information. The bit settings for
these registers are shown in Figure A-109 and described in Table A-110.
6DIR_MUTEMute.
0 = Mute disabled
1 = Mute serial data outputs, maintaining clocks (digital black)
7DIR_PLLDISDisable PLL. Determines clock input for S/PDIF receiver.
0 = Use derived clock from the digital PLL
1 = Use clock input from external PLL
8Reserved
9DIR_RESETReset S/PDIF Receiver. By default, the S/PDIF receiver is always
enabled. If this bit is set, the S/PDIF receiver and digital PLL are
disabled.
10 Reserved
11 DIR_DTS_CD_
4K_EN
DTS_CD 4096 Frames Support Enable. If this bit is set,
and if NON-AUDIO preamble is detected, then the
DIR_NOAUDIOLR bit is asserted high and remains high if
another NON AUDIO preamble is detected within 4096 frames,
otherwise it is cleared. The assertion and deassertion of
DIR_NOAUDIO bit can generate the DIR_NOAUDIO_INT
DAI interrupt, if unmasked in the
DAI_IRPTL_FE/DAI_IRPTL_RE interrrupt mask registers.
This bit is supported with on-chip Digital PLL only. This bit is
applicable only for the ADSP-2147x and ADSP-2148x proces-
sors.
31–12 Reserved
Table A-109. DIRCTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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