DDR2 DRAM Controller (ADSP-2146x)
3-46 ADSP-214xx SHARC Processor Hardware Reference
Force Load Mode Register
Programs can use the Force LMR command by setting bit 22 (=1) in the
SDCTL register. This command is preceded by a precharge all (if banks not
idle) followed by a mode register write.
The Force LMR bit allows changes to the MODE register based settings dur-
ing runtime. These settings include the CL (CAS latency) timing
specification which needs to be changed to adapt to a new frequency
operation.
Force Auto-Refresh
Bit 20 (=1) forces the auto refresh to be immediately executed (not wait-
ing until the refresh counter has expired). This is useful for test purposes
but also to synchronize the refresh time base with a system relevant time
base.
DDR2 DRAM Controller (ADSP-2146x)
The DDR2 DRAM controller on ADSP-2146x processors enable a trans-
fer of data to and from synchronous DDR2 DRAM. It supports a glueless
interface with four external banks, controlled by the memory chip select
pins (DDR2_CS3–0), of standard DDR2 DRAMs of 256 Mbit to 2 Gbit
with configurations x8 and x16.
Features
The features of the DDR2 DRAM controller are listed below.
• I/O width 16-bits, I/O supply 1.8 V
• Supports DDR2-400 of 256M bit, 512M bit, 1G bit and 2G bit
with configurations of x8 and x16
• Supports page sizes of 512, 1K, 2K, and 4K words
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