Data Transfers
10-40 ADSP-214xx SHARC Processor Hardware Reference
transfers to/from the serial port buffers (
TXSPxA, TXSPxB, RXSPxA, and
RXSPxB).
Data Buffers
When programming the serial port channel (A or B) as a transmitter, only
the corresponding TXSPxA and TXSPxB buffers become active while the
receive buffers
RXSPxA and RXSPxB remain inactive. Similarly, when the
SPORT channel A and B are programmed as receive-only the correspond-
ing
RXSPxA and RXSPxB are activated. Do not attempt to read or write to
inactive data buffers. If the processor operates on the inactive transmit or
receive buffers while the SPORT is enabled, unpredictable results may
occur.
Word lengths of less than 32 bits are automatically right-justified
in the receive and transmit buffers.
Transmit Buffers (TXSPxA/B)
The transmit buffers (TXSP7–0A, TXSP7–0B) are the 32-bit transmit data
buffers for SPORT7–0 respectively. These buffers must be loaded with the
data to be transmitted if the SPORT is configured to transmit on the A
and B channels. The data is loaded automatically by the DMA controller
or loaded manually by the program running on the processor core.
The transmit buffers act like a two-location buffer because they have a
data register plus an output shift register. Two 32-bit words may both be
stored in the transmit queue at any one time. When the transmit register is
loaded and any previous word has been transmitted, the register contents
are automatically loaded into the output shifter. An interrupt occurs when
the output transmit shifter has been loaded, signifying that the transmit
buffer is ready to accept the next word (for example, the transmit buffer is
not full). This interrupt does not occur when serial port DMA is enabled
or when the corresponding mask bit in the
LIRPTL/IRPTL register is set.
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