ADSP-214xx SHARC Processor Hardware Reference 6-25
FFT/FIR/IIR Hardware Modules
Vertical FFT Configuration
6. Configure a coefficient DMA to read 2V twiddle factors from the
vertical coeff buffer into the accelerator (total of 2V 32-bit words)
and wait until the DMA is complete (or chain DMA in Step 7).
This step is not needed if twiddles are already in the coefficient
memory of the accelerator.
7. Configure a data transmit DMA to load 2N – 1 data points from
the input buffer into the accelerator with a modify value of 2H,
and a circular buffer length of 2N – 1. Chain a data transmit DMA
of count = 1 that loads the last imaginary point.
The FFT_CPACKIN/FFT_CPACKOUT settings are not applicable for
N ≥ 512 points. The input is always expected to be in alternate real
and imaginary format and the output is always generated in the
same format.
8. Configure a data receive DMA to read 2N data points from the
accelerator into the special buffer with a modify of 1. There is no
need to wait until the DMA in Step 6 completes.
Special Buffer Configuration
9. Configure a DMA to load special coefficients from the special coef-
ficients buffer into the accelerator, with a count = 512.
10.Once the DMA in Step 9 completes, configure a data DMA
(chained or via interrupt) to read 256 data points (count = 256)
from the special buffer into the accelerator with a modify value = 1.
11.Configure a data DMA to write 256 data points (count = 256)
from the accelerator into the special buffer with modify value = 1.
There is no need to wait until the DMA in Step 9 completes.
12.Repeat step 9 N/128 times (offset processing the entire 2N buffer
of data).
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