ADSP-214xx SHARC Processor Hardware Reference A-47
Registers Reference
AMI Control Registers (AMICTLx)
The AMICTL0–3 registers control the mode of operations for the four banks
of external memory. These registers are shown in Figure A-21 and
described in Table A-26. Note for all AMI timing bit settings, all defined
cycles are derived from the SDRAM clock.
14–12 FRZCR Arbitration Freezing Length for CORE Accesses.
000 = No Freezing
001 = 4 Accesses
010 = 8 Accesses
011 = 16 Accesses
100 = 32 Accesses
101 = Page size (SDRAM only
1
)
110, 111 = Reserved
18–15 DATEN EP Data Mask Enable. In no pack mode of the SDRAM/AMI
memory controller, masks those bits of the data lane (DL)
with zeros. The data lane is 8 bits. The 16-bit data bus has
two data lanes.
DATA31–24 is reserved
DATA23–16 is reserved
DATA15–8 is mapped to DATEN1
DATA7–0 is mapped to DATEN0
For example, if DATEN is 0011, then DL1 and DL01 are
masked with zeros.
31–19 Reserved
1 The EPCTL register automatically reads the SDCTL page size setting (SDCAW), programs just
need to program the EPCTL for selecting page size freeze mode.
Table A-25. EPCTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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