Peripherals Routed Through the DPI
A-254 ADSP-214xx SHARC Processor Hardware Reference
Clock Divider Register (TWIDIV)
During master mode operation, the SCL clock divider register (
TWIDIV
shown in Figure A-144 and described in Table A-137) values are used to
create the high and low durations of the serial clock (SCL). Serial clock fre-
quencies can vary from 400 KHz to less than 20 KHz. The resolution of
the clock generated is 1/10 MHz or 100 ns.
Table A-136. TWIMITR Register Bit Descriptions (RW)
Bit Name Description
0–6 PRESCALE Prescale. The number of peripheral clock (PCLK) periods used in the
generation of one internal time reference. The value of PRESCALE must
be set to create an internal time reference with a period of 10 MHz. This
is represented as a 7-bit binary value.
7TWIEN
TWI Enable. This bit must be set for slave or master mode operation. It
is recommended that this bit be set at the time PRESCALE is initialized
and remain set. This guarantees accurate operation of bus busy detection
logic.
0 = Disable TWI
1 = Enable TWI master and slave mode operation
Figure A-144. TWIDIV Register
Table A-137. TWIDIV Register Bit Descriptions (RW)
Bit Name Description
7–0 CLKLOW Clock Low. Number of internal time reference periods the serial clock
(TWI_CLK) is held low. Represented as an 8-bit binary value.
15–8 CLKHI Clock High. Number of internal time reference periods the serial
clock (TWI_CLK) waits before a new clock low period begins (assum-
ing a single master). Represented as an 8-bit binary value.
CLKLOW (7–0)
CLKHI (15–8)
09 837564 2114 12 11 101315
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