ADSP-214xx SHARC Processor Hardware Reference 3-21
External Port
ing 1 to the
SDPSS bit in the SDCTL register, subsequent SDRAM accesses
initiate the power-up sequence. The exact order of the power-up sequence
is determined by the SDPM bit of the SDCTL register.
The load mode register command initializes the following parameters.
• Burst length = 1, bits 2–0, always zero
• Wrap type = sequential, bit 3, always zero
• Ltmode = latency mode (CAS latency), bits 6–4, programmable in
the SDCTL register
• Bits 14–7, always zero
While executing the load mode register command, the unused address
pins are set to zero. During the first SDCLK cycle following load mode reg-
ister, the SDC issues only NOP commands to satisfy the t
MRD
specification.
Bank Activation
The bank activation command is required for first access to any internal
bank in SDRAM. This command open a row in the particular bank for
the subsequent access. The value on the ADDR18–17 pins selects the bank.
And the address provided on the ADDR15–0 pins selects the row. This row
remains open for access until a single precharge command is issued to that
bank. The single precharge command must be issued before opening a dif-
ferent row in the same bank.
Single Precharge
For a page miss during reads or writes in any specific internal SDRAM
bank, the SDC uses the single precharge command to close that bank. All
other internal banks are untouched.
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